• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In einem vierdrahtseitig parallel zu einer Gabelschaltung (G) liegenden Übersprech- u/o. Echokompensationssignalspeicher (KS) wird im Verlauf einer Serie von isolierten Sendesignalimpulsen (s) das im Vierdrahtleitungs-Empfangszweig (VE) auftretende Übersprech- u./o. Echosignal sukzessive A-codiert in einem Umlaufregister (UR1) als Teilkompensationssignal in AM-Darstellung abgespeichert, und in weiteren Umlaufregistern (...URr) werden durch bereits abgespeicherte Teilkompensationssignale teilkompensierte Übersprech- u./o. Echosignale nachfolgender isolierter Sendesignalimpulse (s) als weitere Teilkompensationssignale abgespeichert.
    公开号:SU1605937A3
    申请号:SU823445700
    申请日:1982-05-28
    公开日:1990-11-07
    发明作者:Бирт Винфрид
    申请人:Сименс Аг (Фирма)；
    IPC主号:
    专利说明:

    The invention can be used in digital communication systems when transmitting signals to eliminate MJex.
    The aim of the invention is to improve the accuracy of compensation.
    The drawing shows a block diagram of an apparatus for carrying out the method.
    The device contains act of terrorism 1, differential system 2, reception path 3, accumulator A of compensation signals, block 5 of the control recording of compensation signals, block 6 of the control of reading compensation signals, block 7 for estimating and summing up, decisive block 8, two-wire path 9 and reversing counter 10. The accumulator of compensation signals consists of N write switches 11.1-11.N and N cyclic registers 12.1-12.N of shift,
    The evaluation and summation unit consists of R switching elements 13.1-13.NR and NR resistors 14.1-14.NR.
    The device works in the following way.
    Signals from the transmitting path 1 through the differential system 2 enter the receiving path 3. In case the two-wire line has reflections that appear in places where the parameters of the line change abruptly, the echo signals of the transmitting signals appear, moreover In the case of limited attenuation in the obstacle band of the differential system, the signals from the transmitting path 1 may partially enter the receiving unit. At the same time, the mixed signal consisting of the receiving signal and the interfering signal from the echo and / or a transient signal. This
    signal interference and must be compensated for.
    To compensate for such a signal interference to the melody of the transmitting and receiving paths provided for use. the accumulator of the co-efficient signals, 0 controlled from the blocks 5 and 6 of the control recording and reading of the compensation signals. The drive 4 compensation signals has N cyclic registers 12.1-12.N shift, 5 the number of bits of which is determined by n-5fatny (with n 1, 2, 3, ...) time bits of the transmitted signal, and which follow each other with intervals corresponding to the time Q-bits of the transmitted signal. The accumulator 4 of compensation signals is connected by means of an evaluation and summation unit 7 of a control controlled from a control unit 6, and implemented in a form of a switching grid of resistors 14.1-14.N, whose resistance varies, for example, according to rule 1 (5 RI). variable value from cyclic shift register to cyclic shift register. The evaluation and summation unit 7 inputs a compensation signal into the receiving path 3.
    45 The cyclic registers of the 12.1-12.N shift are recorded partial compensation signals, which each time the supply voltage is applied to the digital communication system are stored in the memory 4. In this case, an echo and / or a transition signal is recorded in the first cyclic shift register 12.1, corresponding to the transmitting signal, quantize and encode, as a partial compensation signal, the signal already partially compensated by means of 50 is sequentially recorded in the next cyclic shift register 12.2
    55
    written in cyclic shift register 12.1.
    The reading of the cyclic shift registers 12.1-12. N is carried out by the second control unit 6, which can be performed on the same shift registers as the storage shift register 4, but with a different clock cycle. readout. The capacity of the shift registers is relatively small and depends on the read cycle with which the echo and / or transient signal is read to form a compensation signal and is subjected to quantization and encoding. The higher the read frequency, the smaller the quantization distortion and the more accurate the compensation.
    The degree of error reduction increases linearly with increasing shear cycles, but exponentially with increasing number of shift registers. As cyclic registers 12.1-12. N shift can be used as shift registers with the same, and with different numbers of bits.
    To record the individual partial compensation signals E, the shift registers are connected to the receiving path 3 by means of write switches 11.1-11.NR, controlled from control unit 5.
    When reading a certain number of echo and / or transient signals at the same moment of time, an average value is formed, which, by means of a reversible counter 10 3-recorded through switches 11.1-11.NR, write to shift registers 12.1-12.N. At each such transmitting signal, an echo and / or transient signal appears in the receiving branch of the four-wire line to which, when approaching the receiving path 3, a compensation signal is transmitted coming from accumulator A and the estimator and summation unit and then to the input of the decision block 8 a signal is provided consisting of the difference of the echo and / or transition signal and the compensation signal. .
    If at the same time the registers of 12.1-12.N shift of accumulator 4 are completely empty, a completely uncompensated signal appears at the input of the decision block 8, which, depending on this read value, causes O or 1 reversible counter 10, located in
    0
    five
    middle position. Upon repeated repetition of this process, an average value of the echo and / or transition signal is formed, which by means of the switch 11.1 of the record controlled by the control unit 5 records the first digit of the shift register 12.1.
    Then, the echo and / or transient signals, extracted from the transmitting signals, are read out at the second time instant, and the signal element corresponding to the average value goes to the control inputs of the decisive signal.
    block 8 and through the corresponding the switching element controlled by the control unit 5 is recorded in the second bit of the shift register 12.1.
    In the course of a whole partial series of isolated transmission signals, the corresponding echo and / or transition signals are read out at subsequent time points and the result is sequentially encoded to form a partial compensation signal recorded in the subsequent shift register bits 12.1.
    The shift register 12.1 records the total directly corresponding echo and / or transient signal to the transmitting signal, quantized and encoded as a partial compensation signal, which can act as a coarse compensation of the echo and / or transition signal
    whereby the latter uses damping, expressed respectively in order with term 2aig |, where d is equal to the number of polling steps per transmission step, for example, 14 dB.
    This partial compensation signal is then used to supplement the nearest bit of the shift register for coarse compensation. The partial compensation signal is then used for coarse coordination when forming the next partial compensation signal in the next shift register. This happens as described.
    权利要求:
    Claims (12)
    [1]
    1. Method of generating and accumulating a signal for compensating transition
    0
    five
    0
    and / or echo interference between the transmitting and receiving paths of the four-wire channel, consisting in transmitting test nMx pulses to the transmitting path, receiving response signals in the receiving path, and storing the response signals. and with the fact that, in order to compensate accuracy, the signals
    About | tklika quantized, encoded, and eapominin & n in the form of partial compensation-Hbix signals, formed by kom p; sensation of response signals with a previous h | an actual compensation signal.
    [2]
     2. The method according to p. 1, differs - 1c | u and with the fact that the signal response to | is woven at different times with subsequent coding and storing in; neighboring cells
    [3]
    : 3. The method according to p. 1, about tl and h a - y | y and so that delta modulation is used for encoding.
    [4]
    4. The method according to claim 1, wherein, when quantizing consecutive response signals
    AT; the same time received signal | al is averaged.
    [5]
    5. The method according to claim 1, wherein the O1 coding is performed in variable pitch.
    [6]
    6. The method according to claim 1, which differs from 10 times and so that with each shutdown, the method of generating and accumulating a signal for transient Schomech is repeated.
    [7]
    7. Method according to claim 1, characterized in that the compensation signal is constantly changing.
    [8]
    8. A device for generating and accumulating a signal to compensate for transient and / or echo interference between the transmitting and receiving paths of the four-wire channel containing the transmitting and receiving paths, in which the input path of the receiving path and the output of the transmitting path are connected to a differential system. , as well as the unit of evaluation and summation, the output of which is connected to the input of the receiver path
    Q
    e
    0
    five
    Q
    d
    five
    a driver channel, a compensation signal accumulator, the output of which is connected to an evaluation and summation unit, as well as a control unit for reading compensation signals, the input of which is connected to the transmitting path of a four-wire channel, which is different. the fact that the compensation signal accumulator contains accumulators of partial compensation signals, whose inputs through recording switches, the control inputs of which are connected to the outputs of the control block of recording compensation signals, are connected to the receiving path of the four-wire channel, and the accumulators of partial compensation signals are designed as cyclic shift registers , the number of bits of which is determined by a multiple of (where n is 1, 2, 3, ...) the bit time of the transmitted signal, and the outputs of the shift registers are Nena evaluation unit and summation.
    [9]
    9. The device according to claim 8, characterized in that a reversible counter is connected between the receiving path of the four-wire channel and the recording switches.
    [10]
    10. The device according to claim 8, characterized in that the cyclic shift registers have a different number of bits.
    [11]
    11. The device according to claim 8, characterized in that the evaluation and summing unit is made in the form of a switching grid of resistors, the resistance values of which are stepwise from 1.1 from the cyclic shift register to the cyclic shift register.
    [12]
    12. The device according to claim 8, wherein the evaluation unit and the circuit are in the form of a switching grid of capacitors whose capacitance varies in steps from the cyclic register to the cyclic register.
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    同族专利:
    公开号 | 公开日
    DE3121545A1|1982-12-23|
    AU554002B2|1986-08-07|
    DE3121545C2|1986-12-04|
    AT22635T|1986-10-15|
    ZA823769B|1983-03-30|
    BR8203166A|1983-05-17|
    EP0066006A3|1984-01-11|
    LU83692A1|1982-02-18|
    JPS57203354A|1982-12-13|
    EP0066006A2|1982-12-08|
    AU8428082A|1982-12-02|
    EP0066006B1|1986-10-01|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    CH423875A|1964-07-23|1966-11-15|Gretag Ag|Method and device for the transmission of messages over channels of limited bandwidth|
    US3426281A|1966-02-28|1969-02-04|Us Army|Reception of time dispersed signals utilizing impulse response storage in recirculating delay lines|
    JPS5728982B2|1974-09-03|1982-06-19|
    US4024358A|1975-10-31|1977-05-17|Communications Satellite Corporation |Adaptive echo canceller using differential pulse code modulation encoding|
    NO140648C|1977-10-24|1983-03-29|Elektrisk Bureau As|DIRECTIVE CONNECTOR.|
    JPS5829023B2|1978-07-10|1983-06-20|Fujitsu Kk|
    DE2853167C2|1978-12-08|1980-10-30|Siemens Ag, 1000 Berlin Und 8000 Muenchen|Subscriber circuit|
    JPS6214144B2|1979-03-16|1987-03-31|Fujitsu Ltd|
    DE2920575C2|1979-05-21|1981-09-17|Siemens AG, 1000 Berlin und 8000 München|Digital telecommunications system with at least one four-wire line section|
    DE3116863C2|1981-04-28|1985-08-08|Siemens AG, 1000 Berlin und 8000 München|Circuit arrangement for digital signal echo cancellation|CA1186029A|1982-06-11|1985-04-23|Gordon F. Mein|Automatic correction circuit for received digitallyencoded signals|
    DE3327467A1|1983-07-29|1985-02-14|Siemens AG, 1000 Berlin und 8000 München|METHOD AND CIRCUIT ARRANGEMENT FOR COMPENSATING ECHO SIGNALS|
    GB2144950A|1983-08-10|1985-03-13|Philips Electronic Associated|Data transmission system|
    JPH0886241A|1994-09-16|1996-04-02|Hitachi Ltd|Drive device for sensor and actuator|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    DE3121545A|DE3121545C2|1981-05-29|1981-05-29|Crosstalk and / or Echo cancellation circuit|
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